******************* FILE 6 of 6 FILES **********************

(C) 31 JUL 88

Eric Gustafson,  N7CL
2018 S. Avenida Planeta
Tucson, AZ 85710



          DPLL  Derived Data Carrier Detect (DCD)
          For Filter Based and Single Chip Modems


                              Figure 1

            ASCII Representation of DCD Circuit Schematic


       //=================7 wire BUS * ================\\
      ||                                                ||
+5 V>-----------+--+---------------+--+--+--+--+----------------+-----+
supply||        |  +---|(---G      |  |  |  |  |        ||    __|___  |
      ||        |     10uF         |  |  |  |  |        ||   | 14   | |
      || +------+------+      +----+--+--+--+--+------+ ||   |      | |
      |\-| 3   20     2|------|10  28 27 26 23 1    11|-/|   | U3   | |
      |\-| 4          5|------| 9                   12|-/|   |74HC14| |
      |\-| 7   U1     6|------| 8         U2        13|-/|   |      | |
      |\-| 8          9|------| 7                   15|-/|   |__7___| |
      |\-|13 74HC374 12|------| 6       27C64       16|-/|      |     |
      |\-|14         15|------| 5                   17|-/|      G     |
       \-|17         16|------| 4                   18|-/             |
DATA>----|18 11 10 1 19|------| 3 25 24 22 21 20  2 19|--/\/\/\/---+  |
from     +---+--+--+---+      +----+--+--+--+--+--+---+    4.7K    |  |
modem chip   |  |  |               |  |  |  |  |  |                |  |
             |  |  |               |  |  |  |  |  |           +----+  |
CLK >--------+  +--+               +--+--+--+--+--+           |       |
input from         |               |                          |  Q1   |   Q2
X16 or X32 baud    G               G                          |     E-+-E
clock source                                                  |   |/ 2N  \|
                                                              +-B-| 3906  |-B-+
GND >---G                                                         |\ (2) /|   |
                                                                    C-+-C     |
                                 1N4148                               |       |
DCD <--------+                +----|<|----+        +------------------+       |
out     U3D  |   U3C     U3B  |           |   U3A  |                          |
___    8 /|9 |  6 /|5   4 /|3 |   220K    |  2 /|1 |   470K                   |
LED <--o< |--+--o< |--+-o< |--+--/\/\/\/--+--o< |--+--/\/\/\/--G              |
out      \|       \|  |   \|  |                \|  |                          |
___                   |       |   0.47uF           |   0.1uF                  |
DCD <-----------------+       +----|(-----G        +----|(-----G              |
out         100K                                                              |
       +--/\/\/\/--G                                                          |
       |  U3F                                                                 |
       |13|\12                           __                    10K            |
 CD >--+--| >o------+------------------< CD  <---------+-----/\/\/\/----------+
from      |/        |                   JMP1           |
modem               |                 (AMD7910)        |
chip                |  11|\10                          |
                    +----| >o----------< CD  <---------+
                         |/             JMP2
                        U3E           (TCM3105)

                NOTE:  Only JMP1 OR JMP2 installed NOT both!

                    *  BUS wire connections are in order
                       vertically.  Top pin goes to top
                       pin bottom pin goes to bottom pin
                       etc.

EOT
EOF